Semiconductor memories with cells in bipolar or merged transistor logic (MTL) technology are known in principle. In commonly assigned U.S. Pat. No. 4,280,198, filed Dec. 7, 1979, by K. Heuber and S. K. Wiedmann, a discharge process is described for such memories, which permits discharging capacitive currents on particular lines for faster reading and writing. MTL cells are described, for example, in commonly assigned United Kingdom Pat. No. 1,569,800 filed Mar. 2, 1977, by S. K. Wiedmann.
In addition, it is usual for the row and word lines of bipolar and FET memories to be divided into two parts. Such a memory is described, for example, in U.S. Pat. No. 3,959,781, filed by R. J. Mehta and M. Geilhufe on Nov. 4, 1974. This memory is characterized in that the row lines have right and left partitions, that a number of sense amplifiers corresponding to the number of row lines are arranged in a column such that each of the amplifiers connects a right row line partition to a left row line partition, that the cells each comprise one field-effect transistor having its gate connected to the column lines and its source or drain to one of the row lines, and one capacitive element, that furthermore several auxiliary cells are provided, one of which is connected to one of the right or the left row line partitions, and that an input/output bus is arranged at and connected to one end of the row lines, the bus being such as to be connectable to the cells for the sense amplifiers. As the word circuits are arranged in the center of the left and the right word line, the effective word line capacity is halved. In spite of this, the word line capacity is still too high, particularly for memories with a very large number of cells per word line, so that such an approach is not suitable for very large scale integrated memories with a very high information storage capacity. As the word lines are selected only after having been discharged, there is a reduction in speed and there are very high capacitive currents leading to increased dissipation and noise problems in the matrix.
The obvious solution of dividing the entire memory matrix into several partial matrices is disadvantageous for very large scale integration because of the large number of peripheral circuits required which in turn lead to increased area equirements, dissipation power and highly complex wiring of the partial matrices.
Another solution for reducing the dissipation power and for rendering effective only particular memory parts required is described in commonly assigned U.S. Pat. No. 3,599,182, filed Jan. 15, 1969, by R. A. Henle, relating to a data storage with a plurality of storage locations, an address register and a decoder for addressing one storage location in each case for the purpose of reading stored or entering new information. This data storage is characterized in that the decoder comprises a main decoder, connected to the address register through address signal lines, and a group of decoders following the main decoder, which are all connected in parallel to further address signal lines of the address register, and that each of the decoders is associated with a switch unit for selectively connecting the respective decoder to the operating voltage, and each of the output lines of the main decoder is connected to a control node of the switch unit of one of the following decoders such that if the decoder is addressed by the address register, a signal appearing on one of the output lines of the main decoder causes only that decoder to be activated whose switch unit is connected to the respective output line. This circuit, too, has the disadvantage that the line capacities are still insufficiently low to permit short access times in very large scale integrated memories with a very high storage capacity.
To double the capacity of a memory, commonly assigned U.S. patent application having Ser. No. 423,983, filed by L. Arzubi on Sept. 27, 1982, concerns a solution for a field-effect transistor memory, wherein the outputs of the sense latch are connected to two pairs of cross-coupled charge storage elements as bit line coupling transistors, and wherein bit line pairs of double the magnitude are connected to the charge coupling elements. An additional bit line for controlling the additional cells is arranged in separate partitions, each partition having its own reference cells and being connected to the sense latch through layers, acting as low- capacity lines, and to charge coupling elements. Although, in this case, by using a second metallization layer for wiring purposes and by utilizing the self-isolating characteristics of the latches acting as read amplifiers, the number of bits per bit line is doubled without having to increase the cell size and without unduly reducing the read signal such that more peripherial circuits are required, an extension of the word lines and the specific problems related therewith is neither illustrated nor indicated, so that this approach is equally unsuitable for very large scale integrated memories with a very high storage capacity.